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VLSI-Design of Non-Volatile Memories

E-BookPDF1 - PDF WatermarkE-Book
582 Seiten
Englisch
Springer Berlin Heidelbergerschienen am06.12.20052005
The electronics and information technology revolution continues, but it is a critical time in the development of technology. Once again, we stand on the brink of a new era where emerging research will yield exciting applications and products destined to transform and enrich our daily lives! The potential is staggering and the ultimate impact is unimaginable, considering the continuing marriage of te- nology with fields such as medicine, communications and entertainment, to name only a few. But who will actually be responsible for transforming these potential new pr- ucts into reality? The answer, of course, is today's (and tomorrow's) design en- neers! The design of integrated circuits today remains an essential discipline in s- port of technological progress, and the authors of this book have taken a giant step forward in the development of a practice-oriented treatise for design engineers who are interested in the practical, industry-driven world of integrated circuit - sign.mehr
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Produkt

KlappentextThe electronics and information technology revolution continues, but it is a critical time in the development of technology. Once again, we stand on the brink of a new era where emerging research will yield exciting applications and products destined to transform and enrich our daily lives! The potential is staggering and the ultimate impact is unimaginable, considering the continuing marriage of te- nology with fields such as medicine, communications and entertainment, to name only a few. But who will actually be responsible for transforming these potential new pr- ucts into reality? The answer, of course, is today's (and tomorrow's) design en- neers! The design of integrated circuits today remains an essential discipline in s- port of technological progress, and the authors of this book have taken a giant step forward in the development of a practice-oriented treatise for design engineers who are interested in the practical, industry-driven world of integrated circuit - sign.
Details
Weitere ISBN/GTIN9783540265009
ProduktartE-Book
EinbandartE-Book
FormatPDF
Format Hinweis1 - PDF Watermark
FormatE107
Erscheinungsjahr2005
Erscheinungsdatum06.12.2005
Auflage2005
Seiten582 Seiten
SpracheEnglisch
IllustrationenXXVIII, 582 p.
Artikel-Nr.1431747
Rubriken
Genre9200

Inhalt/Kritik

Inhaltsverzeichnis
1;Preface;5
2;Acknowledgements;7
3;Contents;8
4;Foreword: Non- Volatile Memory Technology Evolution;15
4.1;Systems Needs for Non-Volatile Storage;16
4.2;NOR Flash Memory;19
4.3;NAND Flash Memory;21
4.4;New Memory Concepts;23
4.5;Conclusions;26
5;1 Non-Volatile Memory Design;27
5.1;1.1 Introduction;27
5.2;1.2 Main Features of Non-Volatile Memories;28
5.3;1.3 Program;29
5.4;1.4 Erase;30
5.5;1.5 Distributions and Cycles;30
5.6;1.6 Read Mode Architecture;33
5.7;1.7 Write Mode Architecture;34
5.8;1.8 Erase Mode Architecture;35
5.9;1.9 Elements of Reliability;36
5.10;1.10 Influence of Temperature and Supply Voltage;36
5.11;1.11 Lab Activities;37
5.12;1.12 Working Tools;38
5.13;1.13 Shmoo Plots;40
5.14;1.14 Testing;42
5.15;1.15 Memory Pins Description;42
5.16;Bibliography;45
6;2 Process Aspects;47
6.1;2.1 Introduction;47
6.2;2.2 Main Steps of Fabrication for a CMOS Process;47
6.3;Bibliography;59
7;3 The MOSFET Transistor and the Memory Cell;61
7.1;3.1 The MOSFET Transistor;61
7.2;3.2 Transistors Available;65
7.3;3.3 The Memory Cell;70
7.4;3.4. Reading Characteristics;74
7.5;3.5 Programming;76
7.6;3.6 Program Algorithm;83
7.7;3.7 Erase Operation;85
7.8;3.8 Erase Algorithm;94
7.9;Bibliography;95
8;4 Passive Components;97
8.1;4.1 MOS Capacitors;97
8.2;4.2 CMOS Technology Capacitors;99
8.3;4.3 Integrated Resistors;102
8.4;Bibliography;105
9;5 Fundamental Circuit Blocks;106
9.1;5.1 Introduction;106
9.2;5.2 NMOS and CMOS Inverters;106
9.3;5.3 The Cascode;112
9.4;5.4 Differential Stage;115
9.5;5.5 The Source Follower;119
9.6;5.6 Voltage References;121
9.7;5.7 Current Mirrors;131
9.8;5.8 NMOS and CMOS Schmitt Trigger;134
9.9;5.9 Voltage Level Shifter Latch;139
9.10;5.10 Power On Reset Circuits;140
9.11;5.11 Analog Switch;144
9.12;5.12 Bootstrap;148
9.13;5.13 Oscillators;156
9.14;5.14 Circuits to Detect Third Level Signals;160
9.15;5.15 VDD Low Detector;162
9.16;Bibliography;163
10;6 Layout;165
10.1;6.1 Custom Layout;165
10.2;6.2 A Three-Inputs NAND;165
10.3;6.3 A Three-Inputs NOR;168
10.4;6.4 An Interdigitized Inverter and a Capacitor;168
10.5;6.5 Area and Perimeter Parasitic Capacitances;170
10.6;6.6 Automatic Layout;171
10.7;Bibliography;173
11;7 The Organization of the Memory Array;175
11.1;7.1 Introduction: EPROM Memories;175
11.2;7.2 Flash Memory Organization: The Sectors;175
11.3;7.3 An Array of Sectors;182
11.4;7.4 Other Types of Array;183
11.5;Bibliography;189
12;8 The Input Buffer;190
12.1;8.1 A Discussion on Input and Output Levels;190
12.2;8.2 Input Buffers;191
12.3;8.3 Examples of Input Buffers;193
12.4;8.4 Automatic Stand-By Mode;195
12.5;Bibliography;197
13;9 Decoders;198
13.1;9.1 Introduction;198
13.2;9.2 Word Line Capacitance and Resistance;202
13.3;9.3 Row Decoders;207
13.4;9.4 NMOS Row Decoder;213
13.5;9.5 CMOS Row Decoders;216
13.6;9.6 A Dynamic CMOS Row Decoding;218
13.7;9.7 A Semistatic CMOS Row Decoder;220
13.8;9.8 Row Decoders for Low Supply Voltage;222
13.9;9.9 Row Pre-Decoder at High Voltage;225
13.10;9.10 Sector Decoding;226
13.11;9.11 Memory Space for Test: The OTP Rows;228
13.12;9.12 Hierarchical Row Decoding;229
13.13;9.13 Low Switching Consumption Row Decoder;234
13.14;9.14 Column Decoders;236
13.15;Bibliography;238
14;10 Boost;240
14.1;10.1 Introduction;240
14.2;10.2 Boost Techniques;240
14.3;10.3 One-Shot Local Boost;243
14.4;10.4 Double-Boost Row Decoder;247
14.5;10.5 The Issue of the Recharge of CBOOST;250
14.6;10.6 Double-Path Boost Circuitry;253
14.7;10.7 Boosted Voltages Switch;256
14.8;10.8 Leakage Recovery Circuits;259
14.9;Bibliography;261
15;11 Synchronization Circuits;262
15.1;11.1 ATD;262
15.2;11.2 Multiple ATD Management;264
15.3;11.3 Let´s Connect the ATD to the Boost Circuitry;266
15.4;11.4 Equalization of the Sense Amplifier: SAEQ;268
15.5;11.5 The ENDREAD Signal;273
15.6;11.6 The Cells Used by the Dummy Sense Amplifiers;275
15.7;11.7 ATD - ENDREAD Overlap;275
15.8;11.8 Sequential Reads;276
15.9;Bibliography;290
16;12 Reading Circuits;291
16.1;12.1 The Inverter Approach;291
16.2;12.2 Differential Read with Unbalanced Load;295
16.3;12.3 Differential Reading with Current Offset;299
16.4;12.4 Semi-Parallel Reference Current;301
16.5;12.5 Techniques to Speed Up Read;305
16.6;12.6 Differential Read with Current Mirror;309
16.7;12.7 The Flash Cell;311
16.8;12.8 Reading at Low VDD;312
16.9;12.9 Amplified I/V Converter;315
16.10;12.10 Amplified Semi-Parallel Reference;316
16.11;12.11 Sizing of the Main Mirror;318
16.12;12.12 Dynamic Analysis of the Sense Amplifier;320
16.13;12.13 Precharge of the Output Stage of the Comparator;323
16.14;12.4 Issues of the Reference;324
16.15;12.15 Mirrored Reference Current;326
16.16;12.16 The Verify Operation;328
16.17;Bibliography;331
17;13 Multilevel Read;334
17.1;13.1 Multilevel Storage;334
17.2;13.2 Current Sensing Method;336
17.3;13.3 Multilevel Programming;339
17.4;13.4 Current/Voltage Reference Network;340
17.5;13.5 Voltage Sensing Method;343
17.6;13.6 Sample & Hold Sense Amplifier;346
17.7;13.7 Closed-Loop Voltage Sensing;350
17.8;13.8 Hierarchical Row Decoding for Multiple Sensing Loops;353
17.9;13.9 A/D Conversion;356
17.10;13.10 Low Power Comparator;359
17.11;Bibliography;361
18;14 Program and Erase Algorithms;363
18.1;14.1 Memory Architecture from the Program-Erase Functionality Point of View;363
18.2;14.2 User Command to Program and Erase;366
18.3;14.3 Program Algorithm for Bi-Level Memories;367
18.4;14.4 Program Algorithm for Multilevel Memories;371
18.5;14.5 Erase Algorithm;376
18.6;14.6 Test Algorithms;379
18.7;Bibliography;380
19;15 Circuits Used in Program and Erase Operations;381
19.1;15.1 Introduction;381
19.2;15.2 Dual Voltage Devices;382
19.3;15.3 Charge Pumps;384
19.4;15.4 Different Types of Charge Pumps;390
19.5;15.5 High Voltage Limiter;401
19.6;15.6 Charge Pumps for Negative Voltages;403
19.7;15.7 Voltage Regulation Principles;404
19.8;15.8 Gate Voltage Regulation;404
19.9;15.9 Drain Voltage Regulation and Temperature Dependence;421
19.10;Bibliography;426
20;16 High-Voltage Management System;428
20.1;16.1 Introduction;428
20.2;16.2 Sectors Biasing;428
20.3;16.3 Local Sector Switch;433
20.4;16.4 Stand-By Management;436
20.5;16.5 High-Voltage Management;442
20.6;16.6 Modulation Effects;448
20.7;Bibliography;459
21;17 Program and Erase Controller;461
21.1;17.1 FSM Controller;461
21.2;17.2 STD Cell Implementation of the FSM;462
21.3;17.3 PLA Implementation of the FSM;463
21.4;17.4 Microcontroller;465
21.5;Bibliography;472
22;18 Redundancy and Error Correction Codes;473
22.1;18.1 Redundancy;473
22.2;18.2 Redundancy & Read Path;475
22.3;18.3 Yield;477
22.4;18.4 UPROM Cells;482
22.5;18.5 The First Read After Power On Reset;488
22.6;18.6 Error Correction Codes;491
22.7;Bibliography;496
23;19 The Output Buffer;499
23.1;19.1 Introduction;499
23.2;19.2 NMOS Output Buffer;502
23.3;19.3 A CMOS Super Output Buffer;503
23.4;19.4 The High Voltage Tolerance Issue;506
23.5;19.5 Noise Induced on the Signal Circuitry by Commutation of the Output Buffers;511
23.6;Bibliography;519
24;20 Test Modes;520
24.1;20.1 Introduction;520
24.2;20.2 An Overview on Test Modes;520
24.3;20.3 DMA Test;522
24.4;20.4 Fast DMA;524
24.5;20.5 Oxide Integrity Test;524
24.6;Bibliography;526
25;21 ESD & Latch-Up;527
25.1;21.1 Notes on Bipolar Transistors;527
25.2;21.2 Latch-Up;532
25.3;21.3 Bipolar Transistors Used in Flash Memories;534
25.4;21.4 Distribution of Power Supplies and ESD Protection Network;536
25.5;Bibliography;539
26;22 From Specification Analysis to Floorplan Definition;540
26.1;22.1 Introduction;540
26.2;22.2 Matrix Organization;540
26.3;22.3 Matrix Row Dimensioning;545
26.4;22.4 Dimensioning the Sectors;548
26.5;22.5 Memory Configurations;550
26.6;22.6 Organization of Column Decoding;551
26.7;22.7 Redundancy;553
26.8;22.8 First Considerations on Read Mode;555
26.9;22.9 Architecture of the Reference;557
26.10;22.10 Read Problems for a Non-Static Memory;558
26.11;22.11 Erase and Program Circuits;559
26.12;22.12 Pad Placement;562
26.13;22.13 Control Logic and Related Circuitry;564
26.14;Bibliography;565
27;23 Photo Album;566
27.1;23.1 Introduction;566
27.2;23.2 Figures Index;566
27.3;23.3 The Photos;567
28;Subject Index;590mehr