Produkt

KlappentextDigital photography, MP3, digital video, etc. make extensive use of NAND-based Flash cards as storage media. To realize how much NAND Flash memories pervade every aspect of our life, just imagine how our recent habits would change if the NAND memories suddenly disappeared. To take a picture it would be necessary to find a film (as well as a traditional camera...), disks or even magnetic tapes would be used to record a video or to listen a song, and a cellular phone would return to be a simple mean of communication rather than a multimedia console. The development of NAND Flash memories will not be set down on the mere evolution of personal entertainment systems since a new killer application can trigger a further success: the replacement of Hard Disk Drives (HDDs) with Solid State Drives (SSDs). SSD is made up by a microcontroller and several NANDs. As NAND is the technology driver for IC circuits, Flash designers and technologists have to deal with a lot of challenges. Therefore, SSD (system) developers must understand Flash technology in order to exploit its benefits and countermeasure its weaknesses. Inside NAND Flash Memories is a comprehensive guide of the NAND world: from circuits design (analog and digital) to Flash reliability (including radiation effects), from testing issues to high-performance (DDR) interface, from error correction codes to NAND applications like Flash cards and SSDs.

Details

Weitere ISBN/GTIN9789048194315

ProduktartE-Book

EinbandartE-Book

FormatPDF

Format Hinweis1 - PDF Watermark

FormatE107

Verlag

Springer Netherlands

Erscheinungsjahr2010

Erscheinungsdatum27.07.2010

Auflage2010

Seiten582 Seiten

SpracheEnglisch

IllustrationenX, 582 p.

Artikel-Nr.1718243

Rubriken

Genre9200

Inhalt/Kritik

Inhaltsverzeichnis

1;Preface;6
2;Acknowledgements;8
3;Table of contents;10
4;1 Market and applications for NAND Flash memories;12
4.1;1.1 Introduction;12
4.2;1.2 Flash memory architectures;13
4.3;1.3 Multi-bit per cell storage;16
4.3.1;1.3.1 Memories scaling;16
4.3.2;1.3.2 Multi-level cell concept;16
4.3.3;1.3.3 NAND scaling;17
4.3.4;1.3.4 Capacity;18
4.3.5;1.3.5 Device characteristics;19
4.4;1.4 Market and applications;21
4.4.1;1.4.1 Removable portable storage;21
4.4.2;1.4.2 Embedded storage;21
4.4.3;1.4.3 Solid state drives;24
4.5;1.5 Market outlook;28
5;2 NAND overview: from memory to systems;30
5.1;2.1 Introduction;30
5.2;2.2 NAND memory;31
5.2.1;2.2.1 Array;31
5.2.2;2.2.2 Basic operations;33
5.2.2.1;Read;34
5.2.2.2;Program;35
5.2.2.3;Erase;36
5.2.3;2.2.3 Logic organization;38
5.2.4;2.2.4 Pinout;39
5.3;2.3 Command set;40
5.3.1;2.3.1 Read operation;40
5.3.2;2.3.2 Program operation;44
5.3.3;2.3.3 Erase operation;46
5.3.4;2.3.4 Synchronous operations;47
5.4;2.4 NAND-based systems;49
5.4.1;2.4.1 Memory controller;51
5.4.1.1;Wear leveling;52
5.4.1.2;Garbage collection;52
5.4.1.3;Bad block management;53
5.4.1.4;ECC;54
5.4.2;2.4.2 Multi-die systems;55
5.4.3;2.4.3 Die stacking;56
5.4.4;2.4.4 3D memories and XLC storage;61
5.5;References;63
6;3 Program and erase of NAND memory arrays;65
6.1;3.1 Floating gate cell physics;65
6.1.1;3.1.1 The ONO IPD floating gate cell;66
6.1.2;3.1.2 The band diagram of the floating gate cell;67
6.1.3;3.1.3 Capacitive cell model;68
6.2;3.2 Altering the stored charges;70
6.2.1;3.2.1 Fowler-Nordheim tunneling mechanism;70
6.2.2;3.2.2 Incremental step pulse programming ISPP;72
6.2.3;3.2.3 Interaction between cell parameters and ISPP;75
6.3;3.3 The NAND array;76
6.4;3.4 The program operation and its side effects in the NAND array;77
6.4.1;3.4.1 Self-boosted program inhibit SBPI;78
6.4.2;3.4.2 Capacitive model of the NAND string;80
6.4.3;3.4.3 Disturb effects;81
6.4.3.1;3.4.3.1 Program disturb;82
6.4.3.2;3.4.3.2 Pass disturb;83
6.4.3.3;3.4.3.3 Edge disturb;83
6.4.4;3.4.4 Advanced SBPI schemes;83
6.4.4.1;3.4.4.1 Local SBPI schemes;84
6.4.4.2;3.4.4.2 Asymmetric SBPI;85
6.5;3.5 The erase operation and the NAND array;87
6.5.1;3.5.1 Self-boosted erase inhibit SBEI;87
6.5.2;3.5.2 Erase disturb;87
6.6;3.6 Stochastic effects: Impact on cell distributions;88
6.6.1;3.6.1 Process variations;88
6.6.2;3.6.2 Floating gate cross-coupling;90
6.6.3;3.6.3 Injection statistics;92
6.6.4;3.6.4 Models for Cell-System Interaction;93
6.7;References;94
7;4 Reliability issues of NAND Flash memories;99
7.1;4.1 Introduction;99
7.2;4.2 Basic concepts;99
7.3;4.3 Basic reliability effects related to tunnel oxides;101
7.3.1;4.3.1 Endurance and intrinsic oxide degradation;101
7.3.2;4.3.2 Hot Hole Injection oxide degradation;103
7.3.3;4.3.3 Data retention;105
7.3.4;4.3.4 Overprogramming;107
7.3.5;4.3.5 General comments concerning oxide degradation;108
7.4;4.4 Disturbs related to memory architecture;109
7.5;4.5 Emerging reliability threats;111
7.5.1;4.5.1 Gate Induced Drain Leakage;111
7.5.2;4.5.2 Random Telegraph Noise;114
7.5.3;4.5.3 Charge injection statistics;117
7.5.4;4.5.4 Temperature instabilities;120
7.6;References;122
8;5 Charge trap NAND technologies;124
8.1;5.1 Introduction;124
8.2;5.2 Planar charge trap NAND;124
8.2.1;5.2.1 Stack description;124
8.2.2;5.2.2 Cell write mechanisms;126
8.2.2.1;Program;128
8.2.2.2;Erase;129
8.2.3;5.2.3 Stack options;130
8.2.4;5.2.4 Why charge trap memories?;133
8.2.5;5.2.5 Planar charge trap issues;134
8.3;5.3 3D charge trap memories;134
8.4;Acknowledgments;136
8.5;References;137
9;6 Control logic;139
9.1;6.1 Logic device view;139
9.2;6.2 Command interface;141
9.3;6.3 Test interface;145
9.4;6.4 Datapath;148
9.5;6.5 Microcontroller;151
9.6;6.6 ROM;158
9.7;6.7 RAM;160
9.8;6.8 Meta-language;161
9.9;References;166
10;7 NAND DDR interface;168
10.1;7.1 NAND Flash evolution: the need for increased bandwidth;168
10.1.1;7.1.1 Applications driving the NAND high speed interface evolution;169
10.1.2;7.1.2 Limitations of the asynchronous interface;170
10.1.3;7.1.3 How to improve the performance of NAND based systems;172
10.1.4;7.1.4 Adopting DDR protocol;173
10.1.5;7.1.5 High density systems: density, power and performance;176
10.2;7.2 Basic input output circuit design;179
10.2.1;7.2.1 I/O circuits for asynchronous NAND;179
10.2.2;7.2.2 Basic CMOS output buffer design;180
10.2.3;7.2.3 Driving high capacitive loads and noise: slew rate control;182
10.2.4;7.2.4 Simultaneous Switching Noise (SSN);184
10.3;7.3 High speed NAND I/O design;186
10.3.1;7.3.1 High speed output buffer circuits;187
10.3.2;7.3.2 Double data rate OCD;188
10.3.3;7.3.3 OCD linearity: push-pull and open-drain configurations;189
10.3.4;7.3.4 Slew rate control and bandwidth;192
10.3.5;7.3.5 Voltage domain change: level shifting;194
10.3.6;7.3.6 Jitter sources and duty cycle distortion;195
10.3.7;7.3.7 ESD;196
10.3.7.1;Input and output ESD protections;198
10.3.8;7.3.8 Layout;198
10.3.9;7.3.9 I/O capacitance problem;200
10.4;References;202
11;8 Sensing circuits;204
11.1;8.1 Introduction;204
11.2;8.2 Reading techniques using the bitline capacitor;207
11.2.1;8.2.1 Interleaving architecture;216
11.2.2;8.2.2 Interleaving architecture: page buffer core design;219
11.3;8.3 Reading techniques with time-constant bitline biasing;225
11.3.1;8.3.1 All BitLine (ABL) architecture;227
11.3.2;8.3.2 ABL architecture: sensing design;230
11.4;8.4 ABL versus interleaving architecture;232
11.5;References;238
12;9 Parasitic effects and verify circuits;241
12.1;9.1 Background pattern dependency (BPD);241
12.2;9.2. Reading techniques for negative sensing;244
12.2.1;9.2.1 Conventional negative verify;245
12.2.2;9.2.2 Absolute negative sensing;248
12.2.3;9.2.3 Current sensing;254
12.2.4;9.2.4 Source line read for ABL sensing;256
12.3;9.3 Source line bias error;258
12.3.1;9.3.1 Sensing with source line bias compensation;262
12.3.2;9.3.2 Multi-pass sensing;264
12.4;References;266
13;10 MLC storage;267
13.1;10.1 MLC coding and programming algorithms;267
13.1.1;10.1.1 Full-sequence programming;269
13.1.2;10.1.2 Floating gate coupling reduction;271
13.2;10.2 MLC sensing circuit;274
13.2.1;10.2.1 Read;274
13.2.2;10.2.2 Cache read;277
13.2.3;10.2.3 MLC program/verify operations;282
13.2.4;10.2.4 Check circuits;289
13.2.5;10.2.5 Coarse and fine programming;291
13.3;10.3 Data-load;295
13.3.1;10.3.1 Data-load 1;295
13.3.2;10.3.3 Data-load 3;300
13.4;10.4 Moving read voltages;302
13.5;References;303
14;11 Charge pumps, voltage regulators and HV switches;305
14.1;11.1 Charge pumps;305
14.2;11.2 Read regulator;309
14.3;11.3 Double-supply voltage regulator;314
14.4;11.4 Voltage references;321
14.5;11.5 Internal supply voltage regulator;324
14.6;References;332
15;12 High voltage overview;334
15.1;12.1 Program algorithm;334
15.2;12.2 Erase algorithm;338
15.3;12.3 HV system;342
15.4;12.4 Wordline decoder;346
15.5;12.5 Hierarchical GWL decoder;351
15.6;References;356
16;13 Redundancy;357
16.1;13.1 Redundancy concept;357
16.2;13.2 NAND architecture and redundancy;358
16.3;13.3 Process data failure analysis and redundancy requirements;362
16.3.1;13.3.1 Failure analysis concept;363
16.3.2;13.3.2 EWS substitution;366
16.4;13.4 Redundancy architectures;369
16.4.1;13.4.1 Realtime substitution;369
16.4.2;13.4.2 Software substitution;375
16.5;13.5 Fuse ROM;387
16.6;13.6 NAND block as OTP for redundancy data concept;392
16.7;References;395
17;14 Error correction codes;397
17.1;14.1 Introduction;397
17.2;14.2 Mathematical background;398
17.2.1;14.2.1 Block codes;399
17.2.2;14.2.2 Convolutional codes;402
17.3;14.3 BCH codes;405
17.3.1;14.3.1 Encoding;406
17.3.2;14.3.2 Decoding;407
17.4;14.4 Reed-Solomon codes;410
17.5;14.5 BCH versus Reed-Solomon;411
17.6;14.6 Parallel BCH;413
17.7;14.7 Low-Density Parity-Check (LDPC) code;417
17.7.1;14.7.1 LDPC code decoding algorithm;418
17.7.2;14.7.2 LDPC code construction and encoder/decoder design;420
17.7.3;14.7.3 QC-LDPC code performance evaluation;423
17.8;References;425
18;15 NAND design for testability and testing;427
18.1;15.1 NAND architecture and testing;427
18.1.1;15.1.1 Array testing;429
18.1.2;15.1.2 High voltage pumps testing;430
18.1.3;15.1.3 Read circuitry testing;431
18.2;15.2 NAND Flash memory testing introduction;432
18.2.1;15.2.1 Test phases: first silicon, ramp-up, production;432
18.2.2;15.2.2 NAND Flash test flow introduction;433
18.2.2.1;Wafer level flow;434
18.2.2.2;Back-end flow;434
18.2.2.3;Burn-in;435
18.2.3;15.2.3 Test flow and test time optimization;437
18.2.4;15.2.4 KGD testing;439
18.2.5;15.2.5 BAD Blocks Management;439
18.3;15.3 NAND DFT;440
18.3.1;15.3.1 Special test pads;441
18.3.2;15.3.2 Low Pin Count Testing (LPCT);443
18.3.3;15.3.3 Voltage regulators and trimming;444
18.3.4;15.3.4 Fuse ROM;446
18.3.5;15.3.5 OTP Blocks;446
18.3.6;15.3.6 Test interface;447
18.3.7;15.3.7 Microcontroller as Built In Self Test (BIST) hardware;447
18.3.8;15.3.8 Fail counter;447
18.4;15.4 Fundamental NAND test modes;448
18.4.1;15.4.1 Parallel tests;449
18.4.1.1;Parallel wordline Program;449
18.4.1.2;Parallel erase;449
18.4.1.3;Parallel read;450
18.4.1.4;Parallel program of array and redundancy;450
18.4.2;15.4.2 Margin read;450
18.4.3;15.4.3 Data fail compression;450
18.4.4;15.4.4 Internal Vth search;451
18.4.5;15.4.5 ROM, RAM, Fuse ROM testing;452
18.4.6;15.4.6 Internal clock measurement;452
18.4.7;15.4.7 Tests for defect detection and yield enhancement;453
18.4.7.1;Shorts among bit lines detection;454
18.4.7.2;Bit lines opens, string open;454
18.4.7.3;Shorts between wordlines;454
18.4.8;15.4.8 Stress modes;455
18.5;References;456
19;16 XLC storage;458
19.1;16.1 Introduction;458
19.2;16.2 VTH distribution width;460
19.3;16.3 8LC;462
19.3.1;16.3.1 Program sequence;462
19.3.2;16.3.2 Program: circuits and cache operation;467
19.3.3;16.3.3 Read: circuits and cache operation;472
19.4;16.4 16LC;474
19.4.1;16.4.1 Three rounds re-programming sequence;478
19.4.2;16.4.2 Sequential sensing;480
19.5;References;485
20;17 Flash cards;486
20.1;17.1 Introduction;486
20.2;17.2 Memory card architecture and assembly;487
20.3;17.3 Memory card specifications;489
20.3.1;17.3.1 Pinout;489
20.3.2;17.3.2 Commands and responses;489
20.3.3;17.3.3 Registers;493
20.4;17.4 Flash translation layer;495
20.5;17.5 Cryptography;500
20.6;17.6 Execute in place;502
20.7;17.7 Managed memory;503
20.7.1;17.7.1 Multibit and shrink technology issues;504
20.7.1.1;Read disturb;505
20.7.1.2;Pass disturb;506
20.7.1.3;Program disturb;507
20.7.1.4;Trapping and Detrapping;507
20.7.1.5;Coupling;508
20.7.2;17.7.2 Microcontroller solutions;509
20.7.3;17.7.3 Flexible solution;513
20.8;References;515
21;18 Low power 3D-integrated SSD;517
21.1;18.1 Introduction;517
21.2;18.2 Analysis of SSD performance;518
21.3;18.3 Selective bit-line precharge scheme;522
21.4;18.4 Advanced source-line program;525
21.5;18.5 Intelligent interleaving;527
21.6;18.6 Sector size optimization;529
21.7;18.7 Adaptive program-voltage generator for 3D-SSD;531
21.8;18.8 Conclusions;537
21.9;References;537
22;19 Radiation effects on NAND Flash memories;539
22.1;19.1 Introduction to radiation effects in CMOS circuits;540
22.1.1;19.1.1 Environments;540
22.1.1.1;19.1.1.1 Terrestrial environment;540
22.1.1.2;19.1.1.2 Space;541
22.1.2;19.1.2 Overview of radiation effects;542
22.1.2.1;19.1.2.1 Radiation-matter interaction;542
22.1.2.2;19.1.2.2 Categories of radiation effects;544
22.1.3;19.1.3 Total ionizing dose effects;545
22.1.3.1;19.1.3.1 Basic mechanisms;545
22.1.3.2;19.1.3.2 Effects on MOSFETs;546
22.1.3.3;19.1.3.3 Scaling;547
22.1.4;19.1.4 Single event effects;548
22.2;19.2 Radiation effects on NAND Flash memories;550
22.2.1;19.2.1 Total ionizing dose effects;551
22.2.1.1;19.2.1.1 Floating gate cells;552
22.2.1.2;19.2.1.2 Charge pumps;553
22.2.1.3;19.2.1.3 Decoders;555
22.2.2;19.2.2 Single event effects;556
22.2.2.1;19.2.2.1 Floating gate cells and page buffer;556
22.2.2.2;19.2.2.2 Single event functional interruptions;557
22.2.2.3;19.2.2.3 Power supply current spikes;558
22.2.2.4;19.2.2.4 Overall cross section;559
22.3;19.3 Radiation effects on floating gate cells;560
22.3.1;19.3.1 Total ionizing dose;560
22.3.2;19.3.2 Single event effects;563
22.3.3;19.3.3 Long-term effects;565
22.3.4;19.3.4 Atmospheric neutrons;566
22.4;19.4 Conclusions;567
22.5;References;568
23;About the authors;574
24;Index;575mehr

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