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A Practical Approach to VLSI System on Chip (SoC) Design

E-BookPDF1 - PDF WatermarkE-Book
312 Seiten
Englisch
Springer International Publishingerschienen am25.09.20191st ed. 2020
This book provides a comprehensive overview of the VLSI design process. It covers end-to-end system on chip (SoC) design, including design methodology, the design environment, tools, choice of design components, handoff procedures, and design infrastructure needs. The book also offers critical guidance on the latest UPF-based low power design flow issues for deep submicron SOC designs, which will prepare readers for the challenges of working at the nanotechnology scale. This practical guide will provide engineers who aspire to be VLSI designers with the techniques and tools of the trade, and will also be a valuable professional reference for those already working in VLSI design and verification with a focus on complex SoC designs.

A comprehensive practical guide for VLSI designers;
Covers end-to-end VLSI SoC design flow;
Includes source code, case studies, and application examples.





Dr. Veena S. Chakravarthi has more than two decades of semiconductor industry experience in managing design and development of large multiprocessor SoCs, with around six multimillion gate tape outs to her credit. She obtained her PhD in Electronics Engineering from Bangalore University in 2008. Dr. Chakravarthi is co-founder and Chief Technology Officer of Sensesemi Technologies, a healthcare startup based in Bangalore. Prior to that, she has worked for ITI Limited, Mindtree Consulting Pvt. Ltd., Centillium India Pvt. Ltd., and Transwitch India Pvt. Ltd., and consulted for Ikanos Communications, Pereira Ventures, and Asarva Chips and Technologies in various capacities. She has published many papers and filed two patents in the area of VLSI and healthcare. She has been associated with the research center in the Electronics & Communication Engineering Department at BNM Institute of Technologies, Bangalore. Her areas of research interest include low-power high performance SOC designs in EPON, communication, and wireless technologies. She is currently Vice Chair of the Bangalore Section Chapter of the IEEE Nanotechnology Council, and organized many events including the recent IISc IEEE Nanotechnology Summer School in July 2018.mehr

Produkt

KlappentextThis book provides a comprehensive overview of the VLSI design process. It covers end-to-end system on chip (SoC) design, including design methodology, the design environment, tools, choice of design components, handoff procedures, and design infrastructure needs. The book also offers critical guidance on the latest UPF-based low power design flow issues for deep submicron SOC designs, which will prepare readers for the challenges of working at the nanotechnology scale. This practical guide will provide engineers who aspire to be VLSI designers with the techniques and tools of the trade, and will also be a valuable professional reference for those already working in VLSI design and verification with a focus on complex SoC designs.

A comprehensive practical guide for VLSI designers;
Covers end-to-end VLSI SoC design flow;
Includes source code, case studies, and application examples.





Dr. Veena S. Chakravarthi has more than two decades of semiconductor industry experience in managing design and development of large multiprocessor SoCs, with around six multimillion gate tape outs to her credit. She obtained her PhD in Electronics Engineering from Bangalore University in 2008. Dr. Chakravarthi is co-founder and Chief Technology Officer of Sensesemi Technologies, a healthcare startup based in Bangalore. Prior to that, she has worked for ITI Limited, Mindtree Consulting Pvt. Ltd., Centillium India Pvt. Ltd., and Transwitch India Pvt. Ltd., and consulted for Ikanos Communications, Pereira Ventures, and Asarva Chips and Technologies in various capacities. She has published many papers and filed two patents in the area of VLSI and healthcare. She has been associated with the research center in the Electronics & Communication Engineering Department at BNM Institute of Technologies, Bangalore. Her areas of research interest include low-power high performance SOC designs in EPON, communication, and wireless technologies. She is currently Vice Chair of the Bangalore Section Chapter of the IEEE Nanotechnology Council, and organized many events including the recent IISc IEEE Nanotechnology Summer School in July 2018.
Details
Weitere ISBN/GTIN9783030230494
ProduktartE-Book
EinbandartE-Book
FormatPDF
Format Hinweis1 - PDF Watermark
FormatE107
Erscheinungsjahr2019
Erscheinungsdatum25.09.2019
Auflage1st ed. 2020
Seiten312 Seiten
SpracheEnglisch
IllustrationenXXXII, 312 p. 204 illus.
Artikel-Nr.4888690
Rubriken
Genre9200

Inhalt/Kritik

Inhaltsverzeichnis
1;Foreword;7
2;Foreword;9
3;Foreword;11
4;Preface;13
5;Why This Book?;16
5.1;Why One Should Read This Book?;16
5.2;What Problem Does It Solve?;16
5.3;Who Are the Audience?;17
5.4;What Are the Prerequisites to Read This Book?;17
5.5;Why Become VLSI Designer?;17
5.6;How Is the Book Organized?;18
5.7;References;18
6;Contents;19
7;Abbreviations and Acronyms;25
8;Chapter 1: Introduction;29
8.1;1.1 Introduction to VLSI;29
8.2;1.2 Application Areas of SOC;29
8.3;1.3 Trends in VLSI;30
8.3.1;1.3.1 Complexity;30
8.3.2;1.3.2 VLSI Circuit to System on Chip;31
8.3.3;1.3.3 Speed of Operation;32
8.3.4;1.3.4 Die Size;34
8.3.5;1.3.5 Design Methodology;34
8.4;1.4 SOC Design and Development;36
8.5;1.5 Skill Set Required;36
8.6;1.6 EDA Environment;37
8.7;1.7 Challenges in All;37
8.8;References;38
9;Chapter 2: System on Chip (SOC) Design;39
9.1;2.1 System on Chip (SOC);39
9.2;2.2 Constituents of SOC;39
9.2.1;2.2.1 Processor Cores;42
9.2.2;2.2.2 Embedded Memory Core;44
9.2.3;2.2.3 Analog Cores;44
9.2.4;2.2.4 Interface Cores;44
9.3;2.3 SOC Development Life Cycle;46
9.3.1;2.3.1 SOC Design Requirements;48
9.3.2;2.3.2 Design Strategy;49
9.3.3;2.3.3 SOC Design Planning;49
9.3.4;2.3.4 System Modelling;50
9.3.5;2.3.5 System Module Development Feasibility Study;50
9.3.6;2.3.6 IP Design Decisions;51
9.3.7;2.3.7 Verification IPs;51
9.3.8;2.3.8 Target Technology Decision;51
9.3.9;2.3.9 Development Plan;52
9.3.10;2.3.10 EDA Tool Plan;53
9.4;2.4 Design Center Infrastructure;53
9.4.1;2.4.1 Computational Servers;54
9.4.2;2.4.2 Filers;54
9.4.3;2.4.3 Workstations;55
9.4.4;2.4.4 Backup Servers;55
9.4.5;2.4.5 Source Control Server;55
9.4.6;2.4.6 Firewalls;56
9.4.7;2.4.7 Resource Planning;56
9.5;2.5 SOC Design Flow;56
9.5.1;2.5.1 SOC Chip High-Level Design Methodology;57
9.5.2;2.5.2 Digital SOC Core Development Flow;57
9.5.3;2.5.3 Processor Subsystem Core Design;60
9.5.4;2.5.4 SOC Integrated Design Flow;62
9.5.5;2.5.5 Low-Power SOC Design;62
9.5.6;2.5.6 EVM Design Development Flow;63
9.5.7;2.5.7 Software Development Flow;64
9.5.8;2.5.8 Product Integration Flow;68
10;Chapter 3: SOC Constituents;69
10.1;3.1 Embedded Processor Subsystem for System on Chip;69
10.1.1;3.1.1 Choice of Embedded Processor for SOC;70
10.1.2;3.1.2 Embedded General-Purpose RISC Processors;70
10.1.3;3.1.3 DSP Processors;74
10.1.4;3.1.4 Issues of hw-sw Co-design;75
10.1.5;3.1.5 Processor Subsystems;75
10.1.6;3.1.6 Processor Configuration Tools;76
10.1.7;3.1.7 Development Boards;77
10.2;3.2 Embedded Memories;78
10.2.1;3.2.1 Types of Memories;79
10.2.2;3.2.2 Choice of Memories;79
10.2.3;3.2.3 Memory Compiler and Compiled Memories;79
10.3;3.3 Protocol Blocks;81
10.4;3.4 Mixed Signal Blocks;82
10.5;3.5 RF Control Blocks;84
10.6;3.6 Analog Blocks;84
10.7;3.7 Third-Party IP Cores;85
10.8;3.8 System Software;85
10.8.1;3.8.1 OSI System Model;85
10.8.1.1;Physical Layer (Layer 1);86
10.8.1.2;Data Link Layer (Layer 2);86
10.8.1.3;Network Layer (Layer 3);87
10.8.1.4;Transport Layer (Layer 4);87
10.8.1.5;Session Layer (Layer 5);87
10.8.1.6;Presentation Layer (Layer 6);87
10.8.1.7;Application Layer (Layer 7);87
10.9;3.9 GAMP Classification of Software;87
10.9.1;3.9.1 Hardware;88
10.9.2;3.9.2 Device Driver;88
10.9.3;3.9.3 Firmware;88
10.9.4;3.9.4 Middleware;89
10.9.5;3.9.5 Software;89
10.9.6;3.9.6 Cloud;89
10.10;3.10 Design-Specific Blocks;89
10.11;References;89
11;Chapter 4: VLSI Logic Design and HDL;90
11.1;4.1 VLSI Logic Design Concepts;90
11.1.1;4.1.1 Synchronous Sequential Circuits;90
11.2;4.2 Metastability;92
11.3;4.3 Asynchronous Circuits;92
11.4;4.4 Asynchronous and Synchronous Resets;94
11.5;4.5 Clock Domain Crossovers;94
11.6;4.6 Speed Matching;94
11.7;4.7 Combinational and Synchronous Logic;96
11.8;4.8 Finite State Machines (FSMs);96
11.9;4.9 Standard Cells and Compiled Logic Blocks;97
11.10;4.10 Hard and Soft Macros;97
11.11;4.11 Concept of Buffers;98
11.12;4.12 Hardware Accelerator;98
11.13;4.13 Design Assertions;99
11.14;4.14 Low-Power Design Techniques;99
11.15;4.15 Hardware Description Languages (HDLs);101
11.16;4.16 Behavioral Modelling of the Hardware System;103
11.17;4.17 Dataflow Modelling of the Hardware System;103
11.18;4.18 Structural Modelling of the Hardware System;103
11.19;4.19 Input-Output Pad Instantiation;105
11.19.1;4.19.1 Power Ground Corner Pad Instantiation;107
11.20;References;107
12;Chapter 5: SOC Synthesis;108
12.1;5.1 SOC Synthesis;108
12.1.1;5.1.1 Set Synthesis Environment;111
12.1.2;5.1.2 Read Library;111
12.1.3;5.1.3 HDL Files;111
12.1.4;5.1.4 Elaborate Design Files;112
12.1.5;5.1.5 Read Constraints;112
12.1.6;5.1.6 Optimization Constraint;112
12.1.7;5.1.7 Synthesis;113
12.1.8;5.1.8 Analyze;113
12.1.9;5.1.9 Write Reports;114
12.1.10;5.1.10 Design Constraints;114
12.2;5.2 Design Rule Constraints (DRC);115
12.3;5.3 SOC Design Synthesis;116
12.4;5.4 High Fanout Nets (HFNs);117
12.5;5.5 Low-Power Synthesis;118
12.5.1;5.5.1 Introduction to Low-Power SOCs;118
12.5.2;5.5.2 Universal Power Format (UPF);121
12.6;5.6 Reports;121
12.6.1;5.6.1 Generating an Area Report;123
12.6.2;5.6.2 Gate Level Netlist Verification;123
12.7;References;124
13;Chapter 6: Static Timing Analysis (STA);125
13.1;6.1 SOC Timing Analysis;125
13.2;6.2 Timing Definition;125
13.3;6.3 Timing Delay Calculation Concepts;130
13.4;6.4 Timing Analysis;130
13.5;6.5 Modelling Process, Voltage, and Temperature Variations;135
13.5.1;6.5.1 Equivalent Cells;135
13.6;6.6 Timing and Design Constraints;136
13.7;6.7 Organizing Paths to Groups;138
13.8;6.8 Design Corners;140
13.9;6.9 Challenges of STA During SOC design;141
13.10;Reference;142
14;Chapter 7: SOC Design for Testability (DFT);143
14.1;7.1 Need for Testability;143
14.2;7.2 SOC Design for Testability Guidelines;143
14.3;7.3 DFT Logic Insertion Techniques;146
14.3.1;7.3.1 Scan Insertion;146
14.4;7.4 Boundary Scan;148
14.5;7.5 Boundary Scan Insertion Flow;151
14.6;7.6 Memory Built- In Self-Test (MBIST);151
14.6.1;7.6.1 Stuck-at Faults;154
14.6.2;7.6.2 Transition Faults;154
14.6.3;7.6.3 Coupling Faults;155
14.6.4;7.6.4 Neighborhood Pattern-Sensitive Faults;156
14.6.5;7.6.5 MBIST Algorithms;157
14.7;7.7 ROM Test Algorithm;157
14.8;7.8 Power Aware Test Module Insertion (PATM);158
14.8.1;7.8.1 Logic BIST Insertion;158
14.8.2;7.8.2 Writing Out DFT SDC;161
14.8.3;7.8.3 Compression Insertion;162
14.9;7.9 On-SOC Clock Generation (OSCG) Insertion;162
14.10;7.10 Challenges in SOC DFT;163
14.11;7.11 Memory Clustering;163
14.12;7.12 DFT Simulations;164
14.13;7.13 ATPG Pattern Generation;164
14.14;7.14 Automatic Test Equipment Testing (ATE Testing);164
14.15;7.15 DFT Tools;165
15;Chapter 8: SOC Design Verification;166
15.1;8.1 Importance of Verification;166
15.2;8.2 Verification Plan and Strategies;168
15.3;8.3 Verification Plan;169
15.4;8.4 Functional Verification;171
15.5;8.5 Verification Methods;172
15.6;8.6 Design for Verification;172
15.7;8.7 Verification Example;176
15.8;8.8 Verification Tools;185
15.9;8.9 Verification Language;190
15.10;8.10 Automation Scripts;190
15.11;8.11 Verification Reuse and Verification IPs;191
15.12;8.12 Universal Verification Methodology (UVM);192
15.12.1;8.12.1 Low-Power Design Verification;193
15.12.2;8.12.2 Low-Power Gate-Level Simulation;193
15.13;8.13 Bug and Debug;193
15.13.1;8.13.1 Bug Tracking Workflow;194
15.14;8.14 Formal Verification;194
15.15;8.15 FPGA Validation;196
15.16;8.16 Validation on Development Boards;197
15.17;References;197
16;Chapter 9: SOC Physical Design;198
16.1;9.1 Re-convergent Model of VLSI SOC Design;198
16.2;9.2 File Formats;199
16.3;9.3 SOC Physical Design;199
16.3.1;9.3.1 Physical Design Theory;202
16.3.2;9.3.2 Stick Diagrams;202
16.4;9.4 Physical Design Setup and Floor Plan;208
16.5;9.5 Floor Planning;209
16.6;9.6 Placement;210
16.7;9.7 Physical Design Constraints;211
16.8;9.8 Clock Tree Synthesis (CTS);212
16.9;9.9 Routing;215
16.10;9.10 ECO Implementation;216
16.11;9.11 Advanced Physical Design of SOCs;217
16.11.1;9.11.1 For Low Power;217
16.11.2;9.11.2 For Advanced Technology;219
16.12;9.12 High Performance;219
16.13;9.13 Photolithography and Mask Pattern;220
16.14;References;224
17;Chapter 10: SOC Physical Design Verification;225
17.1;10.1 SOC Design Verification by Formal Verification;225
17.1.1;10.1.1 Model Checking;225
17.1.2;10.1.2 Equivalence Checking;227
17.2;10.2 STA Analysis;229
17.3;10.3 ECO Checks;231
17.4;10.4 Electromigration;231
17.5;10.5 Simultaneous Switching Noise (SSN);231
17.6;10.6 Electrostatic Discharge (ESD) Protection;232
17.7;10.7 IR and Cross Talk Analysis;233
17.8;10.8 Gate-Level Simulation;234
17.9;10.9 Electrical Rule Check (ERC);234
17.10;10.10 DRC Rule Check;235
17.11;10.11 Design Rule Violation (DRV) Checks;235
17.12;10.12 Design Tape-Out;237
17.13;References;238
18;Chapter 11: SOC Packaging;239
18.1;11.1 Introduction to VLSI SOC Packaging;239
18.2;11.2 Classification of Packages;240
18.3;11.3 Criteria for Selection of Packages;240
18.4;11.4 Package Components;241
18.5;11.5 Package Assembly Flow;242
18.6;11.6 Packaging Technology;243
18.7;11.7 Flip-Chip Packages;245
18.8;11.8 Typical Packages;246
18.9;11.9 Package Performance;246
18.10;11.10 System Integration;246
19;Chapter 12: Reference Designs;249
19.1;12.1 Design for Trial;249
19.2;12.2 Prerequisites;249
19.3;12.3 User Guidelines;249
19.4;12.4 Design Directory;250
19.5;12.5 Section 1;250
19.6;12.6 Design Examples;251
19.6.1;12.6.1 32-Bit Adder;251
19.6.2;12.6.2 Test Bench Module adder_tb;252
19.6.3;12.6.3 16 × 16 Multiplier;254
19.7;12.7 32-Bit Counter with Overflow;256
19.7.1;12.7.1 4:2 Encoder;270
19.8;12.8 Section 2;314
19.8.1;12.8.1 Design Flow;314
19.8.2;12.8.2 Executable Scripts;320
19.9;12.9 Section 3;324
19.9.1;12.9.1 Overview and Application Scenario;324
19.9.2;12.9.2 Mini-SOC Design;326
19.9.2.1;IO Diagram;326
20;Index;328mehr

Autor

Dr. Veena S. Chakravarthi has more than two decades of semiconductor industry experience in managing design and development of large multiprocessor SoCs, with around six multimillion gate tape outs to her credit. She obtained her PhD in Electronics Engineering from Bangalore University in 2008. Dr. Chakravarthi is co-founder and Chief Technology Officer of Sensesemi Technologies, a healthcare startup based in Bangalore. Prior to that, she has worked for ITI Limited, Mindtree Consulting Pvt. Ltd., Centillium India Pvt. Ltd., and Transwitch India Pvt. Ltd., and consulted for Ikanos Communications, Pereira Ventures, and Asarva Chips and Technologies in various capacities. She has published many papers and filed two patents in the area of VLSI and healthcare. She has been associated with the research center in the Electronics & Communication Engineering Department at BNM Institute of Technologies, Bangalore. Her areas of research interest include low-power high performance SOC designs in EPON, communication, and wireless technologies. She is currently Vice Chair of the Bangalore Section Chapter of the IEEE Nanotechnology Council, and organized many events including the recent IISc IEEE Nanotechnology Summer School in July 2018.