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High Performance Embedded Architectures and Compilers

E-BookPDF1 - PDF WatermarkE-Book
307 Seiten
Englisch
Springer Berlin Heidelbergerschienen am20.07.20072007
This book constitutes the refereed proceedings of the Second International Conference on High Performance Embedded Architectures and Compilers, HiPEAC 2007, held in Ghent, Belgium, in January 2007. The 19 revised full papers presented together with one invited keynote paper were carefully reviewed and selected from 65 submissions. The papers are organized in topical sections.mehr
Verfügbare Formate
BuchKartoniert, Paperback
EUR53,49
E-BookPDF1 - PDF WatermarkE-Book
EUR53,49

Produkt

KlappentextThis book constitutes the refereed proceedings of the Second International Conference on High Performance Embedded Architectures and Compilers, HiPEAC 2007, held in Ghent, Belgium, in January 2007. The 19 revised full papers presented together with one invited keynote paper were carefully reviewed and selected from 65 submissions. The papers are organized in topical sections.
Details
Weitere ISBN/GTIN9783540693383
ProduktartE-Book
EinbandartE-Book
FormatPDF
Format Hinweis1 - PDF Watermark
FormatE107
Erscheinungsjahr2007
Erscheinungsdatum20.07.2007
Auflage2007
ReiheLecture Notes in Computer Science
Reihen-Nr.4367
Seiten307 Seiten
SpracheEnglisch
IllustrationenXI, 307 p.
Artikel-Nr.8820311
Rubriken
Genre9200

Inhalt/Kritik

Inhaltsverzeichnis
Invited Program.- Keynote: Insight, Not (Random) Numbers: An Embedded Perspective.- I Secure and Low-Power Embedded Memory Systems.- Compiler-Assisted Memory Encryption for Embedded Processors.- Leveraging High Performance Data Cache Techniques to Save Power in Embedded Systems.- Applying Decay to Reduce Dynamic Power in Set-Associative Caches.- II Architecture/Compiler Optimizations for Efficient Embedded Processing.- Virtual Registers: Reducing Register Pressure Without Enlarging the Register File.- Bounds Checking with Taint-Based Analysis.- Reducing Exit Stub Memory Consumption in Code Caches.- III Adaptive Microarchitectures.- Reducing Branch Misprediction Penalties Via Adaptive Pipeline Scaling.- Fetch Gating Control Through Speculative Instruction Window Weighting.- Dynamic Capacity-Speed Tradeoffs in SMT Processor Caches.- Branch History Matching: Branch Predictor Warmup for Sampled Simulation.- Sunflower : Full-System, Embedded Microarchitecture Evaluation.- Efficient Program Power Behavior Characterization.- Generation of Efficient Embedded Applications.- Performance/Energy Optimization of DSP Transforms on the XScale Processor.- Arx: A Toolset for the Efficient Simulation and Direct Synthesis of High-Performance Signal Processing Algorithms.- A Throughput-Driven Task Creation and Mapping for Network Processors.- Optimizations and Architectural Tradeoffs for Embedded Systems.- MiDataSets: Creating the Conditions for a More Realistic Evaluation of Iterative Optimization.- Evaluation of Offset Assignment Heuristics.- Customizing the Datapath and ISA of Soft VLIW Processors.- Instruction Set Extension Generation with Considering Physical Constraints.mehr

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