Produkt

KlappentextDesign for Embedded Image Processing on FPGAs
Bridge the gap between software and hardware with this foundational design reference
Field-programmable gate arrays (FPGAs) are integrated circuits designed so that configuration can take place. Circuits of this kind play an integral role in processing images, with FPGAs increasingly embedded in digital cameras and other devices that produce visual data outputs for subsequent realization and compression. These uses of FPGAs require specific design processes designed to mediate smoothly between hardware and processing algorithm.
Design for Embedded Image Processing on FPGAs provides a comprehensive overview of these processes and their applications in embedded image processing. Beginning with an overview of image processing and its core principles, this book discusses specific design and computation techniques, with a smooth progression from the foundations of the field to its advanced principles.
Readers of the second edition of Design for Embedded Image Processing on FPGAs will also find: Detailed discussion of image processing techniques including point operations, histogram operations, linear transformations, and more
New chapters covering Deep Learning algorithms and Image and Video Coding
Example applications throughout to ground principles and demonstrate techniques

Design for Embedded Image Processing on FPGAs is ideal for engineers and academics working in the field of Image Processing, as well as graduate students studying Embedded Systems Engineering, Image Processing, Digital Design, and related fields.

Donald G. Bailey, PhD, is Professor of Imaging Systems in the Department of Mechanical and Electrical Engineering, Massey University, New Zealand. He is an internationally recognized expert on FPGA technology in image processing and has published widely on FPGAs and related subjects.

Details

Weitere ISBN/GTIN9781119819813

ProduktartE-Book

EinbandartE-Book

FormatEPUB

Format Hinweis2 - DRM Adobe / EPUB

FormatFormat mit automatischem Seitenumbruch (reflowable)

Verlag

John Wiley & Sons

Erscheinungsjahr2023

Erscheinungsdatum08.08.2023

Auflage2. Auflage

Seiten496 Seiten

SpracheEnglisch

Artikel-Nr.12234401

Rubriken

Genre9201

Inhalt/Kritik

Leseprobe

Preface

Image processing, and in particular embedded image processing, faces many challenges, from increasing resolution, increasing frame rates, and the need to operate at low power. These offer significant challenges for implementation on conventional software-based platforms. This leads naturally to considering field-programmable gate arrays (FPGAs) as an implementation platform for embedded imaging applications. Many image processing operations are inherently parallel, and FPGAs provide programmable hardware, also inherently parallel. Therefore, it should be as simple as mapping one onto the other, right? Well, yes â¦and no.

Image processing is traditionally thought of as a software domain task, whereas FPGA-based design is firmly in the hardware domain. There are a lot of tricks and techniques required to create an efficient design. Perhaps the biggest hurdle to an efficient implementation is the need for a hardware mindset. To bridge the gap between software and hardware, it is necessary to think of algorithms not on their own but more in terms of their underlying computational architecture. Implementing an image processing algorithm (or indeed any algorithm) on an FPGA therefore consists of determining the underlying architecture of an algorithm, mapping that architecture onto the resources available within an FPGA, and finally mapping the algorithm onto the hardware architecture. While the mechanics of this process is mostly automated by high-level synthesis tools, the underlying design is not. A low-quality design can only go so far; it is still important to keep in mind the hardware that is being implied by the code and design the algorithm for the underlying hardware.

Unfortunately, there is limited material available to help those new to the area to get started. While there are many research papers published in conference proceedings and journals, there are only a few that focus specifically on how to map image processing algorithms onto FPGAs. The research papers found in the literature can be classified into several broad groups.

The first focuses on the FPGA architecture itself. Most of these provide an analysis of a range of techniques relating to the structure and granularity of logic blocks, the routing networks, and embedded memories. As well as the FPGA structure, a wide range of topics are covered, including underlying technology, power issues, the effects of process variability, and dynamic reconfigurability. Many of these papers are purely proposals, or relate to prototype FPGAs rather than commercially available chips. While they provide insights as to some of the features which might be available in the next generation of devices, most of the topics within this group are at too low a level.

A second group of papers investigates the topic of reconfigurable computing. Here, the focus is on how an FPGA can be used to accelerate some computationally intensive task or range of tasks. While image processing is one such task considered, most of the research relates more to high-performance computing rather than low-power embedded systems. Topics within this group include hardware and software partitioning, hardware and software co-design, dynamic reconfigurability, communications between an FPGA and central processing unit (CPU), comparisons between the performance of FPGAs, graphics processing units (GPUs) and CPUs, and the design of operating systems and specific platforms for both reconfigurable computing applications and research. Important principles and techniques can be gleaned from many of these papers even though this may not be their primary focus.

The next group of papers considers tools for programming FPGAs and applications, with a focus on improving the productivity of the development process. A wide range of hardware description languages have been proposed, with many modelled after software languages such as C, Java, and even Prolog. Many of these are developed as research tools, with very few making it out of the laboratory to commercial availability. There has also been considerable research on compilation techniques for mapping standard software languages to hardware (high-level synthesis). Techniques such as loop unrolling, strip mining, and pipelining to produce parallel hardware are important principles that can result in more efficient hardware designs.

The final group of papers focuses on a range of applications, including image processing and the implementation of both image processing operations and systems. Unfortunately, as a result of page limits and space constraints, many of these papers give the results of the implementation of various systems but present relatively few design details. This is especially so in the case of many papers that describe deep learning systems. Often the final product is described, without describing many of the reasons or decisions that led to that design. Many of these designs cannot be recreated without acquiring the specific platform and tools that were used or inferring a lot of the missing details. While some of these details may appear obvious in hindsight, without this knowledge, many are far from obvious just from reading the papers. The better papers in this group tended to have a tighter focus, considering the implementation of a single image processing operation.

So, while there may be a reasonable amount of material available, it is quite diffuse. In many cases, it is necessary to know exactly what you are looking for, or just be lucky to find it. The intention of this book, therefore, is to bring together much of this diverse research (on both FPGA design and image processing) and present it in a systematic way as a reference or guide.
Intended Audience

This book is written primarily for those who are familiar with the basics of image processing and want to consider implementing image processing using FPGAs. Perhaps the biggest hurdle is switching from a software mindset to a hardware way of thinking. When we program in software, a good compiler can map the algorithm in the programming language onto the underlying computer architecture relatively efficiently. When programming hardware though, it is not simply a matter of porting the software onto hardware. The underlying hardware architecture needs to be designed as well. In particular, programming hardware usually requires transforming the algorithm into an appropriate parallel architecture, often with significant changes to the algorithm itself. This requires significant design, rather than just decomposition and mapping of the dataflow (as is accomplished by a good high-level synthesis tool). This book addresses this issue by not only providing algorithms for image processing operations but also discusses both the design process and the underlying architectures that can be used to implement the algorithms efficiently.

This book would also be useful to those with a hardware background, who are familiar with programming and applying FPGAs to other problems, and are considering image processing applications. While many of the techniques are relevant and applicable to a wide range of application areas, most of the focus and examples are taken from image processing. Sufficient detail is given to make many of the algorithms and their implementation clear. However, learning image processing is more than just collecting a set of algorithms, and there are any number of excellent image processing textbooks that provide these.

It is the domain of embedded image processing where FPGAs come into their own. An efficient, low-power design requires that the techniques of both the hardware engineer and the software engineer be integrated tightly within the final solution.
Changes Since the First Edition

Although many of the underlying design principles have not changed, the environment has changed quite significantly since the first edition. In general, there has been an increase in the requirements within applications. Resolutions are increasing, with high-definition television (HDTV) becoming ubiquitous, and growing demand within 4K and 8K resolutions (the 8K format has 33.2âMpixels). Sensor resolutions are also increasing steadily, with sensors having more than 100âMpixels becoming available. Frame rates have also been increasing, with up to 120âframes per second being part of the standard for ultra-high-definition television (UHDTV). The dynamic range is also increasing from commonly used 8âbits per pixel to 12-16âbits. All of these factors lead to more data to be processed, at a faster rate.

Against this, there has been an increasing awareness of power and sustainability issues. As a low-power computing platform, FPGAs are well placed to address the power concerns in many applications.

The capabilities of FPGAs have improved significantly as technology improvements enable more to be packed onto them. Not only has there been an increase in the amount of programmable logic and on-chip memory blocks, but FPGAs are becoming more heterogeneous. Many FPGAs now incorporate significant hardened logic blocks, including moderately powerful reduced instruction set computing (RISC) processors, external memory interfacing, and a wide range of communication interfaces. Digital signal processing (DSP) blocks are also improving, with the move towards supporting floating-point in high-end devices. Technology improvements have seen significant reductions in the power required.

Even the FPGA market has changed, with the...
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