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SystemVerilog for Verification

A Guide to Learning the Testbench Language Features
BuchGebunden
464 Seiten
Englisch
Springererschienen am14.02.20123. Aufl.
Based on the highly successful second edition, this extended edition of SystemVerilog for Verification: A Guide to Learning the Testbench Language Features teaches all verification features of the SystemVerilog language, providing hundreds of examples to clearly explain the concepts and basic fundamentals.mehr
Verfügbare Formate
BuchGebunden
EUR117,69
BuchKartoniert, Paperback
EUR69,54
E-BookPDF1 - PDF WatermarkE-Book
EUR117,69
E-BookPDF1 - PDF WatermarkE-Book
EUR99,99
E-BookPDF1 - PDF WatermarkE-Book
EUR69,54

Produkt

KlappentextBased on the highly successful second edition, this extended edition of SystemVerilog for Verification: A Guide to Learning the Testbench Language Features teaches all verification features of the SystemVerilog language, providing hundreds of examples to clearly explain the concepts and basic fundamentals.
Zusammenfassung
Details
ISBN/GTIN978-1-4614-0714-0
ProduktartBuch
EinbandartGebunden
Verlag
Erscheinungsjahr2012
Erscheinungsdatum14.02.2012
Auflage3. Aufl.
Seiten464 Seiten
SpracheEnglisch
Gewicht924 g
IllustrationenXLIV, 464 p.
Artikel-Nr.11935869

Inhalt/Kritik

Inhaltsverzeichnis
Verification Guidelines.- Data Types.- Procedural Statements and Routines.- Connecting the Testbench and Design.- Basic OOP.- Randomization.- Threads and Interprocess Communication.- Advanced OOP and Testbench Guidelines.- Functional Coverage.- Advanced Interfaces.- A Complete SystemVerilog Testbench.- Interfacing with C/C++.mehr

Autor


Chris Spear has been working in the ASIC design and verification field for 30 years. He started his career with Digital Equipment Corporation (DEC) as a / CAD Engineer on DECsim, connecting the first Zycad box ever sold, and then a hardware Verification engineer for the VAX 8600, and a hardware behavioral simulation accelerator. He then moved on to Cadence where he was an Application Engineer for Verilog-XL, followed by a stint at Viewlogic. Chris is currently employed at Synopsys Inc. as a Verification Consultant, a title he created a dozen years ago. He has authored the first and second editions of SystemVerilog for Verification: A Guide to Learning the Testbench Language Features . Chris earned a BSEE from Cornell University in 1981. In his spare time, Chris enjoys road biking in the mountains and traveling with his wife.

Greg Tumbush has been designing and verifying ASICs and FPGAs for 13 years. After working as a researcher in the Air Force Research Labs (AFRL) he moved to beautiful Colorado to work with Astek Corp as a Lead ASIC Design Engineer. He then began a 6 year career with Starkey Labs, AMI Semiconductor, and ON Semiconductor where he was an early adopter of SystemC and SystemVerilog. In 2008, Greg left ON Semiconductor to form Tumbush Enterprises, LLC where he has been consulting clients in the areas of design, verification, and backend to ensure first pass success. He is also a part time Instructor at the University of Colorado, Colorado Springs where he teaches senior and graduate level digital design and verification courses. He has numerous publications which can be viewed at www.tumbush.com. Greg earned a Ph.D. from the University of Cincinnati in 1998.
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