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Minimizing and Exploiting Leakage in VLSI Design

Previously published in hardcover
BuchKartoniert, Paperback
214 Seiten
Englisch
Springererschienen am28.11.20142010
This increase in power consumption, coupled with the increasing demand for portable/hand-held electronics, has made power consumption a dominant concern in the design of VLSI circuits today. However, due to current scaling trends, leakage power has now become a major component of the total power consumption in VLSI circuits.mehr
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EUR172,50
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Produkt

KlappentextThis increase in power consumption, coupled with the increasing demand for portable/hand-held electronics, has made power consumption a dominant concern in the design of VLSI circuits today. However, due to current scaling trends, leakage power has now become a major component of the total power consumption in VLSI circuits.
ZusammenfassungThis book presents two techniques to reduce leakage power in digital VLSI ICs. The first reduces leakage through the selective use of high threshold voltage sleep transistors, while the second by applying the optimal Reverse Body Bias voltage.
Details
ISBN/GTIN978-1-4899-8529-3
ProduktartBuch
EinbandartKartoniert, Paperback
Verlag
Erscheinungsjahr2014
Erscheinungsdatum28.11.2014
Auflage2010
Seiten214 Seiten
SpracheEnglisch
Gewicht379 g
IllustrationenXXVII, 214 p.
Artikel-Nr.33573258

Inhalt/Kritik

Inhaltsverzeichnis
Leakage Reduction Techniques: Minimizing Leakage In Modern Day DSM Processes.- Existing Leakage Minimization Approaches.- Computing Leakage Current Distributions.- Finding a Minimal Leakage Vector in the Presence of Random PVT Variations Using Signal Probabilities.- The HL Approach: A Low-Leakage ASIC Design Methodology.- Simultaneous Input Vector Control and Circuit Modification.- Optimum Reverse Body Biasing for Leakage Minimization.- I: Conclusions and Future Directions.- Practical Methodologies for Sub-threshold Circuit Design: Exploiting Leakage Through Sub-threshold Circuit Design.- Exploiting Leakage: Sub-threshold Circuit Design.- Adaptive Body Biasing to Compensate for PVT Variations.- Optimum VDD for Minimum Energy.- Reclaiming the Sub-threshold Speed Penalty Through Micropipelining.- II: Conclusions and Future Directions.- Design of a Sub-threshold BFSK Transmitter IC.- Design of the Chip.- Implementation of the Chip.- Experimental Results.mehr