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Network Processor Design

E-BookPDFDRM AdobeE-Book
336 Seiten
Englisch
Elsevier Science & Techn.erschienen am11.03.2005
The past few years have seen significant change in the landscape of high-end network processing. In response to the formidable challenges facing this emerging field, the editors of this series set out to survey the latest research and practices in the design, programming, and use of network processors.

Through chapters on hardware, software, performance and modeling, Volume 3 illustrates the potential for new NP applications, helping to lay a theoretical foundation for the architecture, evaluation, and programming of networking processors.

Like Volume 2 of the series, Volume 3 further shifts the focus from achieving higher levels of packet processing performance to addressing other critical factors such as ease of programming, application developments, power, and performance prediction. In addition, Volume 3 emphasizes forward-looking, leading-edge research in the areas of architecture, tools and techniques, and applications such as high-speed intrusion detection and prevention system design, and the implementation of new interconnect standards.

*Investigates current applications of network processor technology at Intel, Infineon Technologies, and NetModule.

Presents current research in network processor design in three distinct areas:
*Architecture at Washington University, St. Louis, Oregon Health and Science University, University of Georgia, and North Carolina State University.
*Tools and Techniques at University of Texas, Austin, Academy of Sciences, China, University of Paderborn, Germany, and University of Massachusetts, Amherst.
*Applications at University of California, Berkeley, Universidad Complutense de Madrid, Spain, ETH Zurich, Switzerland, Georgia Institute of Technology, Vrije Universiteit, the Netherlands, and Universiteit Leiden, the Netherlands.
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KlappentextThe past few years have seen significant change in the landscape of high-end network processing. In response to the formidable challenges facing this emerging field, the editors of this series set out to survey the latest research and practices in the design, programming, and use of network processors.

Through chapters on hardware, software, performance and modeling, Volume 3 illustrates the potential for new NP applications, helping to lay a theoretical foundation for the architecture, evaluation, and programming of networking processors.

Like Volume 2 of the series, Volume 3 further shifts the focus from achieving higher levels of packet processing performance to addressing other critical factors such as ease of programming, application developments, power, and performance prediction. In addition, Volume 3 emphasizes forward-looking, leading-edge research in the areas of architecture, tools and techniques, and applications such as high-speed intrusion detection and prevention system design, and the implementation of new interconnect standards.

*Investigates current applications of network processor technology at Intel, Infineon Technologies, and NetModule.

Presents current research in network processor design in three distinct areas:
*Architecture at Washington University, St. Louis, Oregon Health and Science University, University of Georgia, and North Carolina State University.
*Tools and Techniques at University of Texas, Austin, Academy of Sciences, China, University of Paderborn, Germany, and University of Massachusetts, Amherst.
*Applications at University of California, Berkeley, Universidad Complutense de Madrid, Spain, ETH Zurich, Switzerland, Georgia Institute of Technology, Vrije Universiteit, the Netherlands, and Universiteit Leiden, the Netherlands.
Details
Weitere ISBN/GTIN9780080512501
ProduktartE-Book
EinbandartE-Book
FormatPDF
Format HinweisDRM Adobe
Erscheinungsjahr2005
Erscheinungsdatum11.03.2005
Seiten336 Seiten
SpracheEnglisch
Dateigrösse4746 Kbytes
Artikel-Nr.2745504
Rubriken
Genre9200

Inhalt/Kritik

Inhaltsverzeichnis
1;Cover;1
2;Contents;8
3;About the Editors;6
4;Preface;16
5;Chapter 1. Network Processors: New Horizons;18
5.1;1.1 Architecture;20
5.2;1.2 Tools and Techniques;21
5.3;1.3 Applications;22
5.4;1.4 Conclusions;24
5.5;References;24
6;Chapter 2. Supporting Mixed Real-Time Workloads in Multithreaded Processors with Segmented Instruction Caches;26
6.1;2.1 Instruction Delivery in NP Data Processors;28
6.2;2.2 Segmented Instruction Cache;30
6.3;2.3 Experimental Evaluation;34
6.4;2.4 Related Work;46
6.5;2.5 Conclusions and Future Work;47
6.6;References;47
7;Chapter 3. Efficient Packet Classification with Digest Caches;50
7.1;3.1 Related Work;51
7.2;3.2 Our Approach;52
7.3;3.3 Evaluation;59
7.4;3.4 Hardware Overhead;66
7.5;3.5 Conclusions;68
7.6;Acknowledgments;69
7.7;References;69
8;Chapter 4. Towards a Flexible Network Processor Interface for RapidIO, Hypertransport, and PCI-Express;72
8.1;4.1 Interface Fundamentals and Comparison;74
8.2;4.2 Modeling the Interfaces;76
8.3;4.3 Architecture Evaluation;85
8.4;4.4 Conclusions;94
8.5;Acknowledgments;95
8.6;References;95
9;Chapter 5. A High-Speed, Multithreaded TCP Offload Engine for 10 Gb/s Ethernet;98
9.1;5.1 Requirements on TCP Offload Solution;100
9.2;5.2 Architecture of TOE Solution;104
9.3;5.3 Performance Analysis;112
9.4;5.4 Conclusions;114
9.5;Acknowledgments;115
9.6;References;115
10;Chapter 6. A Hardware Platform for Network Intrusion Detection and Prevention;116
10.1;6.1 Design Rationales and Principles;117
10.2;6.2 Prototype NNIDS on a Network Interface;121
10.3;6.3 Evaluation and Results;127
10.4;6.4 Conclusions;132
10.5;References;133
11;Chapter 7. Packet Processing on a SIMD Stream Processor;136
11.1;7.1 Background: Stream Programs and Architectures;137
11.2;7.2 AES Encryption;139
11.3;7.3 IPv4 Forwarding;148
11.4;7.4 Related Work;156
11.5;7.5 Conclusions and Future Work;157
11.6;Acknowledgments;159
11.7;References;159
12;Chapter 8. A Programming Environment for Packet-Processing Systems: Design Considerations;162
12.1;8.1 Problem Domain;164
12.2;8.2 Shangri-La. A Programming Environment for Packet-Processing Systems 150 ;167
12.3;8.3 Design Details and Challenges;169
12.4;8.4 Conclusions;185
12.5;References;186
13;Chapter 9. RNOS A Middleware Platform for Low-Cost Packet-Processing Devices;190
13.1;9.1 Scenario;191
13.2;9.2 Analysis Model of RNOS;192
13.3;9.3 Implementation Model of RNOS;204
13.4;9.4 Measurements and Comparison;209
13.5;9.5 Conclusions and Outlook;210
13.6;Acknowledgments;211
13.7;References;211
14;Chapter 10. On the Feasibility of Using Network Processors for DNA Queries;214
14.1;10.1 Architecture;215
14.2;10.2 Implementation Details;227
14.3;10.3 Results;228
14.4;10.4 Related Work;232
14.5;10.5 Conclusions;233
14.6;Acknowledgments;234
14.7;References;234
15;Chapter 11. Pipeline Task Scheduling on Network Processors;236
15.1;11.1 The Pipeline Task Assignment Problem;238
15.2;11.2 The Greedypipe Algorithm;242
15.3;11.3 Pipeline Design with Greedypipe;245
15.4;11.4 A Network Processor Problem;249
15.5;11.5 Conclusions;259
15.6;Acknowledgments;260
15.7;References;260
16;Chapter 12. A Framework for Design Space Exploration of Resource Efficient Network Processing on Multiprocessor SoCs;262
16.1;12.1 Related Work;264
16.2;12.2 Modeling Packet-Processing Systems;266
16.3;12.3 Scheduling;272
16.4;12.4 Mapping the Application to the System;278
16.5;12.5 Estimating the Resource Consumption;281
16.6;12.6 A Design Space Exploration Example;285
16.7;12.7 Conclusions;292
16.8;Acknowledgments;292
16.9;References;293
17;Chapter 13. Application Analysis and Resource Mapping for Heterogeneous Network Processor Architectures;296
17.1;13.1 Related Work;299
17.2;13.2 Application Analysis;300
17.3;13.3 ADAG Clustering Using Maximum Local Ratio Cut;304
17.4;13.4 ADAG Results;308
17.5;13.5 Mapping Application DAGs to NP Architectures;319
17.6;13.6 Conclusions;323
17.7;References;323
18;Index;326
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