High Performance Memory Systems

von

Hadimioglu, HaldunHrsg.Kaeli, DavidHrsg.Torrellas, JosepHrsg.Nanda, AshwiniHrsg.Kuskin, JeffreyHrsg.

BuchGebunden

Englisch

Springer New Yorkerschienen am31.10.20032004

The State of Memory Technology Over the past decade there has been rapid growth in the speed of micropro cessors. This translates to bit densities increasing at two times every two years until the introduction of 8 gigabit dynamic random access memory (DRAM) chips, after which densities will increase four times every five years.mehr

Verfügbare Formate

BuchGebunden

EUR53,49

BuchKartoniert, Paperback

EUR53,49

E-BookPDF1 - PDF WatermarkE-Book

EUR53,49

Auf dieser Seite:

EUR53,49

In den Warenkorb

Produkt

KlappentextThe State of Memory Technology Over the past decade there has been rapid growth in the speed of micropro cessors. This translates to bit densities increasing at two times every two years until the introduction of 8 gigabit dynamic random access memory (DRAM) chips, after which densities will increase four times every five years.

Details

ISBN/GTIN978-0-387-00310-8

ProduktartBuch

EinbandartGebunden

Verlag

Springer New York

Erscheinungsjahr2003

Erscheinungsdatum31.10.2003

Auflage2004

SpracheEnglisch

MasseBreite 160 mm, Höhe 241 mm, Dicke 21 mm

Gewicht623 g

Artikel-Nr.10555257

Rubriken

GenreComputer/Internet/EDV

Inhalt/Kritik

Inhaltsverzeichnis

1 Introduction to High-Performance Memory Systems - scan all.- 1.1 Coherence, Synchronization, and Allocation.- 1.2 Power-Aware, Reliable, and Reconfigurable Memory.- 1.3 Software-Based Memory Tuning.- 1.4 Architecture-Based Memory Tuning.- 1.5 Workload Considerations.- I Coherence, Synchronization, and Allocation.- 2 Speculative Locks: Concurrent Execution of Critical Sections in Shared-Memory Multiprocessors.- 3 Dynamic Verification of Cache Coherence Protocols.- 4 Timestamp-Based Selective Cache Allocation.- II Power-Aware, Reliable, and Reconfigurable Memory.- 5 Power-Efficient Cache Coherence.- 6 Improving Power Efficiency with an Asymmetric Set-Associative Cache.- 7 Memory Issues in Hardware-Supported Software Safety.- 8 Reconfigurable Memory Module in the RAMP System for Stream Processing.- III Software-Based Memory Tuning.- 9 Performance of Memory Expansion Technology (MXT).- 10 Profile-Tuned Heap Access.- 11 Array Merging: A Technique for Improving Cache and TLB Behavior.- 12 Software Logging under Speculative Parallelization.- IV Architecture-Based Memory Tuning.- 13 An Analysis of Scalar Memory Accesses in Embedded and Multimedia Systems.- 14 Bandwidth-Based Prefetching for Constant-Stride Arrays.- 15 Performance Potential of Effective Address Prediction of Load Instructions.- V Workload Considerations.- 16 Evaluating Novel Memory System Alternatives for Speculative Multithreaded Computer Systems.- 17 Evaluation of Large L3 Caches Using TPC-H Trace Samples.- 18 Exploiting Intelligent Memory for Database Workloads.- Author Index.mehr