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Network Processor Design

E-BookPDFDRM AdobeE-Book
464 Seiten
Englisch
Elsevier Science & Techn.erschienen am02.12.2003
Responding to ever-escalating requirements for performance, flexibility, and economy, the networking industry has opted to build products around network processors. To help meet the formidable challenges of this emerging field, the editors of this volume created the first Workshop on Network Processors, a forum for scientists and engineers to discuss latest research in the architecture, design, programming, and use of these devices. This series of volumes contains not only the results of the annual workshops but also specially commissioned material that highlights industry's latest network processors.

Like its predecessor volume, Network Processor Design: Principles and Practices, Volume 2 defines and advances the field of network processor design. Volume 2 contains 20 chapters written by the field's leading academic and industrial researchers, with topics ranging from architectures to programming models, from security to quality of service.

?Describes current research at UNC Chapel Hill, University of Massachusetts, George Mason University, UC Berkeley, UCLA, Washington University in St. Louis, Link?pings Universitet, IBM, Kayamba Inc., Network Associates, and University of Washington.

?Reports the latest applications of the technology at Intel, IBM, Agere, Motorola, AMCC, IDT, Teja, and Network Processing Forum.
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KlappentextResponding to ever-escalating requirements for performance, flexibility, and economy, the networking industry has opted to build products around network processors. To help meet the formidable challenges of this emerging field, the editors of this volume created the first Workshop on Network Processors, a forum for scientists and engineers to discuss latest research in the architecture, design, programming, and use of these devices. This series of volumes contains not only the results of the annual workshops but also specially commissioned material that highlights industry's latest network processors.

Like its predecessor volume, Network Processor Design: Principles and Practices, Volume 2 defines and advances the field of network processor design. Volume 2 contains 20 chapters written by the field's leading academic and industrial researchers, with topics ranging from architectures to programming models, from security to quality of service.

?Describes current research at UNC Chapel Hill, University of Massachusetts, George Mason University, UC Berkeley, UCLA, Washington University in St. Louis, Link?pings Universitet, IBM, Kayamba Inc., Network Associates, and University of Washington.

?Reports the latest applications of the technology at Intel, IBM, Agere, Motorola, AMCC, IDT, Teja, and Network Processing Forum.
Details
Weitere ISBN/GTIN9780080491943
ProduktartE-Book
EinbandartE-Book
FormatPDF
Format HinweisDRM Adobe
Erscheinungsjahr2003
Erscheinungsdatum02.12.2003
Seiten464 Seiten
SpracheEnglisch
Artikel-Nr.2745505
Rubriken
Genre9200

Inhalt/Kritik

Inhaltsverzeichnis
1;Cover;1
2;Copyright Page;5
3;Contents;8
4;About the Editors;6
5;Preface;16
6;Chapter 1. Network Processors: Themes and Challenges;18
6.1;1.1 Technology;19
6.2;1.2 Programming;20
6.3;1.3 Applications;22
6.4;1.4 Challenges and Conclusions;23
6.5;References;24
7;PART I: DESIGN PRINCIPLES;26
7.1;Chapter 2. A Programmable, Scalable Platform for Next-Generation Networking;28
7.1.1;2.1 The Network Processor Architecture;31
7.1.2;2.2 Processor Scheduling;34
7.1.3;2.3 Fibre Channel/Infiniband Implementation;38
7.1.4;2.4 Performance Simulation and Analysis;40
7.1.5;2.5 Conclusions;43
7.1.6;Acknowledgments;44
7.1.7;References;44
7.2;Chapter 3. Power Considerations in Network Processor Design;46
7.2.1;3.1 Computational Performance Model;49
7.2.2;3.2 Power Model;54
7.2.3;3.3 Performance Metrics;59
7.2.4;3.4 Design Results;60
7.2.5;3.5 Summary and Conclusions;66
7.2.6;Acknowledgments;66
7.2.7;References;66
7.3;Chapter 4. Worst-Case Execution Time Estimation for Hardware-Assisted Multithreaded Processors;68
7.3.1;4.1 Background and Motivation;70
7.3.2;4.2 Processing Throughput of a Single Thread of Execution ;72
7.3.3;4.3 Processing Throughput of Two Threads;76
7.3.4;4.4 Processing Throughput of Four Threads;86
7.3.5;4.5 Limitations and Future Work;86
7.3.6;4.6 Conclusions;88
7.3.7;Acknowledgments;89
7.3.8;References;89
7.4;Chapter 5. Multiprocessor Scheduling in Processor-Based Router Platforms: Issues and Ideas;92
7.4.1;5.1 Related Work and Concepts;94
7.4.2;5.2 Issues in Using Pfair Schedulers in Routers;101
7.4.3;5.3 Multiprocessor Scheduling in Routers: Key Ideas;104
7.4.4;5.4 Experimental Evaluation;111
7.4.5;5.5 Conclusions;113
7.4.6;Acknowledgments;113
7.4.7;References;113
7.5;Chapter 6. A Massively Multithreaded Packet Processor;118
7.5.1;6.1 Random External Memory Accesses;121
7.5.2;6.2 Processor/Memory Architectures;122
7.5.3;6.3 The Tribe Microarchitecture;124
7.5.4;6.4 Network Block;137
7.5.5;6.5 Interconnect;141
7.5.6;6.6 Project Status;145
7.5.7;6.7 Conclusions;146
7.5.8;References;148
7.6;Chapter 7. Exploring Trade-Offs in Performance and Programmability of Processing Element Topologies for Network Processors;150
7.6.1;7.1 Problem Identification ;151
7.6.2;7.2 Performance Modeling and Evaluation ;154
7.6.3;7.3 Topology Exploration for Performance Metrics;163
7.6.4;7.4 Interrelation Between Programmability and Topologies;169
7.6.5;7.5 Conclusions;172
7.6.6;Acknowledgments;173
7.6.7;References;174
7.7;Chapter 8. Packet Classification and Termination in a Protocol Processor;176
7.7.1;8.1 Programmable Protocol Processor;177
7.7.2;8.2 Control Memory Access Accelerator;182
7.7.3;8.3 System Performance;194
7.7.4;8.4 Conclusions;196
7.7.5;8.5 Further Work;196
7.7.6;Acknowledgments;196
7.7.7;References;197
7.8;Chapter 9. NP-Click: A Programming Model for the Intel IXP1200;198
7.8.1;9.1 Background;199
7.8.2;9.2 Programming Models;202
7.8.3;9.3 Description of NP-Click;205
7.8.4;9.4 Results;211
7.8.5;9.5 Summary and Conclusions;215
7.8.6;9.6 Future Work;216
7.8.7;Acknowledgments;217
7.8.8;References;217
7.9;Chapter 10. NEPAL: A Framework for Efficiently Structuring Applications for Network Processors;220
7.9.1;10.1 Modules;223
7.9.2;10.2 NEPAL Design Flow;225
7.9.3;10.3 Module Extraction from Sequential Binaries;226
7.9.4;10.4 Dynamic Module Manager;230
7.9.5;10.5 Discussion;232
7.9.6;10.6 Experiments;233
7.9.7;10.7 Related Work;240
7.9.8;10.8 Conclusions;241
7.9.9;References;242
7.10;Chapter 11. Effcient and Faithful Performance Modeling for Network-Processor-Based System Designs;244
7.10.1;11.1 Approaches to Performance Modeling;246
7.10.2;11.2 Discrete-Event Simulation;248
7.10.3;11.3 Application-Hardware Interface;249
7.10.4;11.4 Modeling Memory Reference Behavior;250
7.10.5;11.5 Time Synchronization;251
7.10.6;11.6 Modeling Multiple Processors;252
7.10.7;11.7 Using Countach for Modeling Network Servers;253
7.10.8;11.8 Performance Evaluation;255
7.10.9;11.9 Conclusions and Ongoing Work;257
7.10.10;References;258
7.11;Chapter 12. High-Speed Legitimacy-Based DDoS Packet Filtering with Network Processors: A Case Study and Implementation on the Intel IXP1200;260
7.11.1;12.1 Background: Legitimacy Tests and Legitimacy List Management ;263
7.11.2;12.2 Prototype Architecture on the Intel IXP1200 Network Processor ;271
7.11.3;12.3 Performance Analysis Experiments;275
7.11.4;12.4 Performance Results;277
7.11.5;12.5 Lessons Learned on Architectural Directions for Network Processors ;283
7.11.6;12.6 Conclusions and Future Work;286
7.11.7;Acknowledgments;287
7.11.8;References;287
7.12;Chapter 13. Directions in Packet Classification for Network Processors;290
7.12.1;13.1 Problem Formulation;292
7.12.2;13.2 IP Prefix Pair Analysis;296
7.12.3;13.3 Transport-Level Field Analysis;306
7.12.4;13.4 Implications;309
7.12.5;13.5 Conclusions;310
7.12.6;Appendix: Derivation of a Tighter Bound on the Number of Partial Overlaps ;311
7.12.7;References;314
8;PART II: PRACTICES;316
8.1;Chapter 14. Implementing High-Performance, High-Value Traffic Management Using Agere Network Processor Solutions;318
8.1.1;14.1 Implementing Traffic Management;319
8.1.2;14.2 10-Gb/s System Solution;321
8.1.3;14.3 5-Gb/s APP550 Solution;337
8.1.4;14.4 Conclusions;342
8.1.5;References;343
8.2;Chapter 15. AMCC nPcore NISC Architecture;344
8.2.1;15.1 The nPcore-based Architecture;344
8.2.2;15.2 Software Architecture;356
8.2.3;15.3 Conclusions;358
8.2.4;References;359
8.3;Chapter 16. Adaptable Bandwidth Allocation for QoS Support in Network Processors;360
8.3.1;16.1 Background;361
8.3.2;16.2 QoS Design for Network Processors;367
8.3.3;16.3 IBM PowerNP QoS Support;376
8.3.4;16.4 Conclusions;379
8.3.5;References;379
8.4;Chapter 17. IDT Network Search Engine with QDR LA-1 Interface;382
8.4.1;17.1 NSE Device Description;383
8.4.2;17.2 Development and System Support Tools;389
8.4.3;17.3 Database Search Solutions, Analysis and Comparison;392
8.4.4;17.4 Conclusion;400
8.4.5;References;400
8.5;Chapter 18. Implementing Voice over AAL2 on a Network Processor;402
8.5.1;18.1 IXP2400 Network Processor;403
8.5.2;18.2 Voice Service Requirements;404
8.5.3;18.3 VoAAL2 Service;404
8.5.4;18.4 Packet Processing in the VoAAL2 Application;406
8.5.5;18.5 QoS Considerations;408
8.5.6;18.6 VoAAL2 Application on IXP2400;410
8.5.7;18.7 Challenges and Lessons Learned;416
8.5.8;18.8 Conclusions;419
8.5.9;References;420
8.6;Chapter 19. Implementing QoS Mechanisms on the Motorola C-Port C-5e Network Processor;422
8.6.1;19.1 The Motorola C-5e Network Processor;423
8.6.2;19.2 Implementing ATM QoS;424
8.6.3;19.3 Implementing diffserv;433
8.6.4;19.4 Design Alternatives;441
8.6.5;19.5 Conclusions;442
8.6.6;References;443
8.7;Chapter 20. A C-Based Programming Language for Multiprocessor Network SoC Architectures;444
8.7.1;20.1 Software Design Considerations;444
8.7.2;20.2 The Teja NP Software Platform;445
8.7.3;20.3 The Teja C Programming Language;446
8.7.4;20.4 Platform Support;455
8.7.5;20.5 Conclusions;458
8.7.6;References;459
9;Index;460
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